1. Field of the Invention
The present invention relates to a parallel precoder circuit that executes an exclusive OR (EXOR) operation on a parallel input, and outputs a parallel output.
2. Description of the Related Art
In recent years, an optical duobinary modulation system and a differential phase shift keying (DPSK) system are calling attention as techniques of increasing a relay distance and increasing a transmission speed, in an optical communication system.
The optical duobinary system narrows a spectrum of a signal by applying a duobinary signal, and can decrease degradation of the signal due to wavelength dispersion. Because a carrier frequency component of the signal decreases, degradation of the signal due to inductive Brillouin scattering can be also decreased.
The duobinary system is classified as partial response (1, 1) in communication engineering, and a transmission and reception system includes a precoder, an encoder, and a decoder. The precoder calculates an EXOR of an input signal and a one-bit delay feedback signal obtained by delaying an output signal of the precoder by one bit, and outputs the calculated result. The encoder adds the output signal of the precoder and the one-bit delay feedback signal obtained by delaying the output signal of the precoder by one bit, and outputs the calculated result. The decoder carries out modulo 2 calculations using the output of the encoder. The precoder circuit is also used as a differential coder that converts the information of “1” and “0” to be communicated into a phase difference between two symbols that are continuously transmitted, in a differential phase shift modulation system.
In the optical duobinary system, a low pass filter achieves the function of the encoder, and a photodetector achieves the function of the decoder in many cases. In other words, individual analog parts and optical elements achieve the functions of the encoder and the decoder in many cases. On the other hand, a logical circuit is usually used for the precoder.
A transmission speed F (hertz) in the optical communication is an ultra-high speed of 10 Gbps and 40 Gbps. Therefore, when a serial precoder circuit that processes a signal as one-bit serial data according to this transmission speed is used, the EXOR circuit to be used is required to operate at an ultra-high speed.
When the transmission speed F becomes an ultra-high speed, a clock unit time per one bit becomes short. Therefore, timing adjustment of a circuit that achieves a one-bit delay becomes difficult.
To solve these problems, a conventional transmission and reception system using a duobinary system converts a serial input signal into a parallel input signal, and a parallel precoder circuit processes the parallel input signal. With this arrangement, the required ultra-high operation speed of the circuit that achieves the function of the precoder can be decreased.
Conventional techniques of a parallel precoder circuit are described in Japanese Patent Application Laid-open No. H11-122205 and Japanese Patent Publication No. 3474794. The conventional parallel precoder circuit described in Japanese Patent Application Laid-open No. H11-122205 operates as follows. To parallelize a signal into n (2≦n, where n is an integer) bit signals, the parallel precoder circuit first inputs the signal to the precoder to a separating circuit, serial-parallel converts the data, or directly uses a parallel signal from a pre-stage circuit such as a framer and develops the signal into an n-bit parallel signal sk(i) (1≦i≦n, where i is an integer), and connects the sk(i) to one of inputs of n two-input EXOR circuits. Next, the parallel precoder circuit connects an output tk(i) of a kth (1≦k≦n−1, where k is an integer) EXOR circuit to the other input of a (k+1)th EXOR circuit, thereby connecting the EXOR circuits in cascade. The parallel precoder circuit delays the output of the nth EXOR circuit by one clock at the operation speed F/n (hertz), and connects this output to the other input of the first EXOR circuit. Finally, a multiplexing circuit parallel-serial converts the outputs of the n EXOR circuits, and outputs the converted data. The parallel precoder circuit that develops the data in parallel operates equivalently to a serial precoder circuit that includes a set of two-input EXOR circuits and a one-clock delay circuit.
According to the conventional parallel precoder circuit described in Japanese Patent Publication No. 3474794, EXOR circuits are connected in cascade like the parallel precoder circuit described in Japanese Patent Application Laid-open No. H11-122205. The parallel precoder circuit inputs branched parallel input signals to multiple-input EXOR circuits, and inputs the outputs of these circuits to a differential encoding circuit The differential encoding circuit has EXOR circuits and a one-clock delay unit. Outputs of the EXOR circuits are input to the one-clock delay unit, and an output of the one-clock delay circuit is input to one EXOR circuit by feedback. An output of the differential encoding circuit is branched, and is also connected to one input of the first EXOR. A time-division multiplexing unit multiplexes the output of the EXOR circuits connected in cascade and the output of the differential encoding circuit, and outputs the multiplexed result. The parallel precoder circuit in this configuration also achieves the equivalent operation of the serial precoder circuit.
However, according to the conventional parallel precoder circuit described in Japanese Patent Application Laid-open No. H11-122205, the path in which a signal is once input to the one-clock delay circuit and passed through all the n EXOR circuits and is input again to the one-clock delay circuit by feedback becomes a maximum delay path that determines an upper limit operation speed of the circuit. In other words, the signal needs to be propagated to the EXOR circuits directly connected at n stages within the one-clock unit time n/F (second) at the operation speed F/n. Therefore, although the input signal is developed into n bits in parallel, a delay time permitted to one EXOR circuit is 1/n. Therefore, individual EXOR circuits must operate at F (hertz), and the effect of the parallelization cannot be obtained sufficiently.
In general, to decrease the number of combined circuits within the maximum delay path (in this case, EXOR circuits), a pipeline method of inserting a flip-flop circuit into between the combined circuits can be used. However, according to the parallel precoder circuit described in Japanese Patent Application Laid-open No. H11-122205, the maximum delay path is a feedback loop in which a signal is once input to the one-clock delay circuit and passed through all the n EXOR circuits and is input again to the one-clock delay circuit by feedback. Therefore, the pipeline method cannot be used in this case.
According to the conventional parallel precoder circuit described in Japanese Patent Publication No. 3474794, the operation speed of the EXOR circuits is relaxed to F/n (hertz), by decreasing the number of stages of the EXOR circuits included in the feedback part to one stage. However, EXOR circuits proportional to the n EXOR circuits connected in cascade remain in order to generate the output of the parallel precoder circuit. When the pipeline system is applied to match the timing of the parallel output signals from the EXOR circuits connected in cascade, flip-flops of the square of n become necessary, which results in a too large circuit scale.
Separately from the conventional parallel precoder circuits described in Japanese Patent Application Laid-open No. H11-122205 and Japanese Patent Publication No. 3474794, there is also a circuit configuration that generates output signals of the parallel precoder circuit from input signals developed in parallel, without using the outputs of EXOR circuits at lower digits within the parallel signals. According to this circuit configuration, the number of stages of the EXOR circuits in the maximum delay path can be decreased. However, according to this circuit configuration, the number of gates of the EXOR circuits, the number of FAN OUTs that branch signal lines, and a wiring length become large. Consequently, the circuit size becomes large in proportion to the square of n.